IEEE P1735/D1, Feb 2023

IEEE P1735/D1, Feb 2023 is a draft recommended practice focused on encryption and management of electronic design intellectual property (IP) in computing and processing systems. It addresses how design assets may be protected and handled when shared across tools, teams, and supply chains, helping reduce exposure of sensitive implementation details. For organizations working with electronic design workflows, the document is relevant to IP control, interoperability, and secure exchange practices.

Overview of IEEE P1735/D1, Feb 2023

This draft technical document provides guidance for protecting electronic design IP through encryption and related management practices. In the context of components, circuits, devices, and systems, IEEE P1735/D1, Feb 2023 is intended to support controlled use of design information while preserving access for authorized development and verification activities. It is commonly associated with design automation workflows where IP must move between suppliers, integrators, and engineering teams without unnecessary disclosure.

Typical use cases

IEEE P1735/D1, Feb 2023 is typically used when engineers need to distribute protected IP blocks, encrypted design files, or model content within electronic design automation flows. It may be relevant for semiconductor design houses, IP vendors, system integrators, and organizations managing reusable circuit or device-level assets. The draft can also support workflows where confidential design content must remain usable in simulation, integration, or verification environments while staying under access control.

Why it matters

Protecting electronic design IP is important for reducing leakage risk, preserving commercial value, and maintaining clear handling rules across design partners. IEEE P1735/D1, Feb 2023 helps define a consistent approach for encryption and management practices, which can improve confidence in file exchange and design collaboration. For procurement, compliance, and engineering governance, a recognized technical reference can also support more predictable evaluation of IP protection methods and associated tooling.

• Encryption of electronic design IP
• Management of protected design assets
• Electronic design automation workflows
• Controlled sharing across engineering teams
• IP protection for circuits and systems