TS EN 60191-6

TS EN 60191-6 sets out the general rules used to prepare outline drawings for surface-mounted semiconductor device packages. Its focus is on how the package outline is represented in technical documentation so that size, shape and mounting-relevant geometry are communicated in a consistent and comparable way across devices.

In general engineering practice, outline drawings are the bridge between a package’s physical form and its documentation. For surface-mount assemblies, they support footprint planning, package identification and mechanical interchangeability discussions. The standard is therefore concerned with mechanical standardization rather than electrical characterization: it helps define how the package is drawn and described, not how the semiconductor functions electrically.

Package families covered by the document

This part supplements IEC 60191-1 and IEC 60191-3. According to the scope, it covers all surface-mounted discrete semiconductors with a lead count of 8 or more, as well as integrated circuits classified as Form E in Clause 3 of IEC 60191-4. In other words, it addresses a defined set of surface-mount package families, not every semiconductor package type.

• General rules for preparing package outline drawings
• A common mechanical description approach for surface-mounted semiconductor devices
• Complementary to IEC 60191-1, IEC 60191-3 and IEC 60191-4
• Applies to discrete devices with 8 or more leads and to Form E integrated circuits